1. Field of the Invention
The present invention concerns a processor data memory address generator.
2. Description of the Prior Art
Programmable electronic systems include a processor which executes instructions supplied by a program controller usually included in the processor. The instructions frequently cause or command operations producing output data addressed to a data memory from input data that may also be stored in said memory. The address of the data memory location for a specific instruction is supplied by an address generator.
A first known data memory addressing technique is direct addressing. In this case the address is supplied directly in the instruction supplied by the program controller.
It is widely accepted that although this technique is very simple it has severe limitations in respect of flexibility. As a result, the execution of a given task by the processor often requires a high number of instructions.
A second known technique is indirect addressing. In this case the address is computed by an address generator from the instruction supplied by the program controller. This technique offers great flexibility in terms of memory organization. The generator includes circuits clocked by a clock signal and combinatory circuits incorporating a large number of cells. Its size is therefore relatively large, whether it comprises registers or an arithmetic and logic unit, for example.
An object of the present invention is an address generator enabling an addressing mode between direct and indirect addressing which, although it does not offer the flexibility of indirect addressing, results in a reduced size and therefore a reduced cost.